*Locations: Athens and Thessaloniki*

Key Responsibilities:

• Develop analog layouts for circuits such as amplifiers, references, bias blocks, and data converters in FinFET nodes
• Apply best practices for DRC/LVS closure, including advanced tips and tricks for efficient debugging
• Perform EM/IR analysis and implement layout changes to meet reliability targets
• Address parasitic effects through careful routing, shielding, and post-extraction corrections
• Implement matching techniques (common-centroid, interdigitation, dummy devices) for precision circuits
• Collaborate with circuit designers to optimize layout for performance and yield
• Ensure compliance with color-aware routing and multi-patterning constraints (SADP/SAQP)

Job Requirements:

• Proven experience in FinFET layout design for analog IP
• Strong knowledge of LDE effects (WPE, STI, LOD) and mitigation strategies
• Proficiency in industry-standard EDA tools (Cadence Virtuoso, Calibre, PVS)
• Familiarity with parasitic extraction flows and correlation techniquesUnderstanding of reliability mechanisms (BTI, HCI) and guard-banding in layout

Preferred Skills:

• Experience with advanced-node design rules and color-aware layout
• Knowledge of EM/IR verification methodologies and sign-off flows
• Ability to automate layout tasks using SKILL or Python scripts